震惊~Signal ＜XXX＞ missing in the sensitivity list is added for synthesis purposes在verilog中警告的解决方法

你是否还在为秃头而烦恼？
你是否还在通宵为了赶项目而焦急？
朋友，你不是 一个人!
看看吧，下面是这个bug的描述：

WARNING:HDLCompiler:91 - "F:\FPGA_Doc\AD_test\uart.v" Line 56: Signal <symbol> missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.

warning这条警告是由于在always@列表中没有出现模块中使用到的变量

always @(state,datain)
begin 
	if(state == 3'b000)
	begin
		uart_data[0] <= 73;//word I;
		uart_data[1] <= 78;//word N;
		uart_data[2] <= 80;//word P;
		uart_data[3] <= 85;//word U;
		uart_data[4] <= 84;//word T;
		uart_data[5] <= 32;//space;
		uart_data[6] <= 86;//word V;
		uart_data[7] <= 79;//word O;
		uart_data[8] <= 76;//word L;
		uart_data[9] <= 84;//word T;
		uart_data[10] <= 65;//word A;
		uart_data[11] <= 71;//word G;
		uart_data[12] <= 69;//word E;
		uart_data[13] <= 58;//symbol :;
		uart_data[14] <= symbol;//symbol;
		uart_data[15] <= datain[15:12] +48; //individual;
		uart_data[16] <= 46;//symbol .;
		uart_data[17] <= datain[11:8] +48;//first digit after dot; //Zero drift recorrection/
		uart_data[18] <= datain[7:4] +48;//second digit after dot;
		uart_data[19] <= datain[3:0] +48;//third digit after dot;
		uart_data[20] <= 86;//word V;
		uart_data[21] <= 13;//symbol /r;
		uart_data[22] <= 10;//symbol /n;
	end
end

那么我们现在添加变量到always@后面的括号中就可以解决问题啦：

always @(state,datain,symbol)

问题解决！