我正在尝试通过 Verilog 实现带有 + 1 逻辑的 D 触发器计数器。但是我收到了很多有关网络多个常量驱动程序的错误代码。有人可以帮我吗？这是到目前为止的代码：
module LAB (clk, clear, Enable, Q);
input clk, clear, Enable;
output[3:0] Q;
reg[3:0] Q;
wire D;
assign D = Q;
always @ (posedge clk)
begin
if (!clear)
Q <= 1'b0;
else
Q <= D;
end
always @ (Enable)
begin
if (Enable == 1)
Q <= D + 1;
else
Q <= D;
end
endmodule
以下是我收到的错误代码：
Error (10028): Can't resolve multiple constant drivers for net "Q[3]" at
LAB.v(17)
Error (10029): Constant driver at LAB.v(9)
Error (10028): Can't resolve multiple constant drivers for net "Q[2]" at LAB.v(17)
Error (10028): Can't resolve multiple constant drivers for net "Q[1]" at LAB.v(22)
Error (10028): Can't resolve multiple constant drivers for net "Q[0]" at LAB.v(22)
Error (12153): Can't elaborate top-level user hierarchy
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 6 errors, 4 warnings
Error: Peak virtual memory: 4613 megabytes
Error: Processing ended: Sun Apr 19 18:39:09 2020
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:00
Error (293001): Quartus II Full Compilation was unsuccessful. 8 errors, 4
warnings
你有2个不同的always驱动相同寄存器的块Q。你可以想一个单独的always块作为单独的硬件设备。因此，在您的情况下，您有 2 个触发器输出已连接。这违反了硬件和综合规则。它还会在模拟过程中产生问题。
解决这个问题的唯一方法是创建一个always块定义了驱动触发器所需的所有逻辑，如下所示：
always @ (posedge clk or negedge clear) begin
if (!clear)
Q <= 1'b0;
else if (enable)
Q <= D + 1;
else
Q <= D;
end
我不是在这里评论你的逻辑，只是给出一个例子，它应该消除多个驱动程序周围的所有错误Q.
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