在 VHDL 中使用 SB_RGBA_DRV 原语

我在使用为 Lattice ICE40UP fpga 提供的 SB​​_RGBA_DRV 原语时遇到问题。 技术库提供了一个 verilog 示例，我可以使用它，但是当我尝试在 VHDL 中使用它时，P&R 失败，输出以下消息：

错误：非法连接：“SB_RGBA_DRV”类型的实例“myrgb”的引脚“RGB2”应仅连接到一个顶部模块端口。它连接到以下终端： LED2_obuf/DOUT0

这是我的 .vhdl 文件：

library ieee;
use ieee.std_logic_1164.all;

entity led is
    port (
        LED0        : out   std_logic;
        LED1        : out   std_logic;
        LED2        : out   std_logic
    );
end entity led;

architecture rtl of led is

component SB_HFOSC is
    port (
        CLKHFEN : in std_logic;
        CLKHFPU : in std_logic;
        CLKHF   : out std_logic 
    );
end component;

component SB_RGBA_DRV is
    generic (
        RGB0_CURRENT: string:="0b000000"; 
        RGB1_CURRENT: string:="0b000000";
        RGB2_CURRENT: string:="0b000000"
    );
    port (  
        RGBPU : in std_logic;
        RGBLEDEN : in std_logic;
        RGB0PWM : in std_logic;
        RGB1PWM : in std_logic;
        RGB2PWM : in std_logic;
        RGB0 : out std_logic;
        RGB1 : out std_logic;
        RGB2 : out std_logic    
        );
end component;

signal int_osc : std_logic;

begin

myosc : SB_HFOSC
    PORT MAP (
        CLKHFEN => '1',
        CLKHFPU => '1',
        CLKHF => int_osc
    );

    myrgb : SB_RGBA_DRV
    GENERIC MAP (
        RGB0_CURRENT => "0b111111",
        RGB1_CURRENT => "0b111111",
        RGB2_CURRENT => "0b111111"
    )
    PORT MAP (
        RGBPU => '1',
        RGBLEDEN => '1',
        RGB0PWM => '1',
        RGB1PWM => '1',
        RGB2PWM => '1',
        RGB0    => LED0,
        RGB1    => LED1,
        RGB2    => LED2
    );

process
    begin
        wait until int_osc'event;
end process;


end rtl;

您的问题的答案在这里：

http://we.easy electronics.ru/teplofizik/podklyuchenie-vstroennogo-modulya-tokovogo-drayvera-fpga-serii-ice5-ice40-ultra.html http://we.easyelectronics.ru/teplofizik/podklyuchenie-vstroennogo-modulya-tokovogo-drayvera-fpga-serii-ice5-ice40-ultra.html

（向下滚动。）是的，是俄语的。关键是在设计文件的顶部添加以下声明：

library sb_ice40_components_syn;
use sb_ice40_components_syn.components.all;

Teplofizik 提到的其他事情可能有助于了解，但并非完全必要。

通过上述添加，您的代码几乎是正确的。我没有尝试构建和运行 Teplofizik 的示例代码，但我确实修改了您的代码（以实际使用片上振荡器），并且该代码很高兴在“iCE40UP Breakout”板上运行：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library sb_ice40_components_syn;
use sb_ice40_components_syn.components.all;

entity led is
    port (
        LED0        : out   std_logic;
        LED1        : out   std_logic;
        LED2        : out   std_logic
    );
end entity led;

architecture rtl of led is

-- not necessary - declared in library
--component SB_HFOSC is
--    port (
--        CLKHFEN : in std_logic;
--        CLKHFPU : in std_logic;
--        CLKHF   : out std_logic 
--    );
--end component;
--
--component SB_RGBA_DRV is
--    generic (
--        RGB0_CURRENT: string:="0b000000"; 
--        RGB1_CURRENT: string:="0b000000";
--        RGB2_CURRENT: string:="0b000000"
--    );
--    port (  
--        RGBPU : in std_logic;
--        RGBLEDEN : in std_logic;
--        RGB0PWM : in std_logic;
--        RGB1PWM : in std_logic;
--        RGB2PWM : in std_logic;
--        RGB0 : out std_logic;
--        RGB1 : out std_logic;
--        RGB2 : out std_logic    
--        );
--end component;

signal int_osc : std_logic;
signal count:   unsigned(25 downto 0);
signal led0_en: std_logic;
signal led1_en: std_logic;
signal led2_en: std_logic;

begin

myosc : SB_HFOSC
    generic map(
        CLKHF_DIV => "0b00"     -- 00 = 48 MHz, 01 = 24 MHz, 10 = 12 MHZ, 11 = 6 MHz
    )
    PORT MAP (
        CLKHFEN => '1',
        CLKHFPU => '1',
        CLKHF => int_osc
    );

    myrgb : SB_RGBA_DRV
    GENERIC MAP (
--        RGB0_CURRENT => "0b111111",
--        RGB1_CURRENT => "0b111111",
--        RGB2_CURRENT => "0b111111"
        CURRENT_MODE => "0b0",      -- 0 = full current, 1 = halve the current
        RGB0_CURRENT => "0b000001", -- 4 mA is more than enough
        RGB1_CURRENT => "0b000001",
        RGB2_CURRENT => "0b000001"
    )
    PORT MAP (
--        RGBPU => '1',     -- this is an SB_RGB_DRV parameter
        CURREN => '1',
        RGBLEDEN => '1',
--        RGB0PWM => '1',   -- boring
--        RGB1PWM => '1',
--        RGB2PWM => '1',
        RGB0PWM => led0_en,
        RGB1PWM => led1_en,
        RGB2PWM => led2_en,
        RGB0    => LED0,
        RGB1    => LED1,
        RGB2    => LED2
    );

    -- boring
--process
--    begin
--        wait until int_osc'event;
--end process;

    -- cycle through LED's

    led0_en <= count(25) and count(24);
    led1_en <= count(25) and not count(24);
    led2_en <= not count(25) and count(24);

    count_proc: process(int_osc)
    begin
        if rising_edge(int_osc) then
            count <= count+1;
        end if;
    end process;

end rtl;