UVM基础知识3：Systemverilog 验证 12.2.2实例

来源：systemverilog验证 测试平台编写指南（书籍）

1 新建counter7.c文件

    vi counter7.c

#include<svdpi.h>
#include<malloc.h>
#include<veriuser.h>


typedef struct {
  unsigned char cnt;
} c7;


void* counter7_new() {
  c7* c = (c7*) malloc(sizeof(c7));
  c-> cnt = 0;
  return c;
}


void counter7(
            c7            *inst,
            svBitVecVal   *count,
    const   svBitVecVal   *i,
    const   svBit         reset,
    const   svBit         load){

  if (reset)      inst -> cnt = 0;
  else if (load)  inst -> cnt = *i;
  else            inst -> cnt++;
  inst -> cnt = inst -> cnt & 0x7f;
  *count = inst -> cnt;

  io_printf("C: count = %d, i= %d, reset = %d, load = %d\n",*count, *i, reset, load);
}

2 新建test.sv

vi test.sv

`timescale 1ns/1ps


import "DPI-C" function chandle counter7_new(); 
import "DPI-C" function void counter7 ( 
    input   chandle   inst,
    output  bit[6:0]  out,
    input   bit[6:0]  in,
    input   bit       reset,load);

import "DPI-C" function real sin(input real r); 

program automatic test;
  
initial begin 
  
  bit [6:0]   o1, o2, i1, i2;
  bit         reset,  load, clk1;
  chandle     inst1,  inst2;

  inst1 = counter7_new();
  inst2 = counter7_new();

  fork
      forever #10 clk1 = ~clk1;
      forever @(posedge clk1) begin 
          counter7(inst1, o1, i1, reset,  load);
          counter7(inst2, o2, i2, reset,  load);
      end 
  join_none

  reset = 0;
  load  = 0;
  i1    = 120;
  i2    = 10;

  @ (negedge clk1);
  load  = 1;

  @ (negedge clk1);
  load  = 0;

  #100 $finish;

end

endprogram

3 新建makefile

vi makefile 

run: vcs sim 

vcs:
	vcs -full64 -sverilog test.sv counter7.c

sim:
	./simv

clean:
	rm -f simv novas.conf *.log *.dump *.rc *.key test.fsdb
	rm -rf csrc/ simv.daidir/ verdiLog/

4 仿真

make run